This invention relates to integrated circuits and more specifically to isolation regions surrounding transistors in a bipolar integrated circuit. This invention also relates to contacts for grounding the substrate of an integrated circuit.
It is known in the art to provide a plurality of bipolar transistors in an integrated circuit and to electrically isolate the transistors so that the operation of one transistor does not interfere with the operation of another transistor. In one prior art structure, a vertical NPN transistor is formed in an epitaxial layer of one conductivity type which in turn is formed on a substrate of the opposite conductivity type. The NPN transistor is laterally surrounded by a P+ region which extends from the surface of the epitaxial layer to an underlying laterally extending PN isolation junction formed between the substrate and the epitaxial layer. This P+ region isolates the NPN transistor from other devices formed within the epitaxial layer. Such a structure is illustrated as prior art in FIGS. 1 and 2 of U.S. Pat. No. 3,648,125, issued to Douglas Peltzer, and incorporated herein by reference. Unfortunately, the P+ isolation region of Peltzer FIGS. 1 and 2 contacts and forms a capacitive PN junction with the collector region of the transistor. The capacitance of this junction degrades the speed of the transistor.
It is also known in the art to isolate a transistor by laterally surrounding the transistor with a silicon dioxide isolation region which extends from the surface of the epitaxial layer to the underlying laterally extending PN isolation junction. Such an isolation structure is disclosed in the Peltzer patent (e.g. Peltzer FIG. 4). It is also known to provide a doped channel stop region under the silicon dioxide isolation region discussed by Peltzer to further isolate adjacent transistors. Unfortunately, this structure does not allow for good electrical contact from the top side to the underlying substrate adjacent to the transistor. Because of this, it is generally necessary for the transistor buried layer to extend beneath the inner edge of the silicon dioxide isolation region to prevent substrate injection current from the transistor collector. This is particularly true in applications in which the transistors are driven into saturation and are sensitive to increases in substrate voltage. (Although Peltzer FIGS. 5 and 6 illustrate a buried layer that does not extend beneath the entire inner edge of the silicon dioxide isolation regions, in such a structure it is usually necessary to use other means for limiting substrate current injection, provide an added substrate contact structure adjacent to the transistor, use the transistor in a substrate voltage insensitive application, or provide a relatively large space between the transistors.) Because the buried layers must generally extend beneath and be in contact with the silicon dioxide isolation regions but be spaced far enough apart so as to avoid contacting the aforementioned channel stop region, this isolation structure consumes a relatively large surface area.
U.S. Pats. Nos. 4,454,646 and 4,454,647 issued to Joy et al. discuss an isolation structure in which a silicon dioxide isolation region laterally surrounds a transistor. The silicon dioxide isolation region extends from the surface of the epitaxial layer to the substrate. Portions of the silicon dioxide isolation region include openings which are filled with P+ type polycrystalline silicon. These P+ regions are used to ground the substrate adjacent to the transistor. Unfortunately, the process used to build this structure is quite complicated.